Technical Field
This invention relates generally to integrated circuit (IC) cell design, and more particularly, to manufacturing approaches for enhanced circuit routing.
Related Art
Computer-aided cell-based design has been developed for designing large scale ICs such as application specific integrated circuits (ASICs) and gate arrays. The cell is a circuit that has been pre-designed and pre-verified as a building block. Design technologies known as standard cell and gate array use different types of such building blocks. In a standard cell design, each distinct cell in a library may have unique geometries of active, gate, and metal levels. Examples of a standard cell or gate array cell include an inverter, a NAND gate, a NOR gate, a flip flop, and other similar logic circuits.
During the process of designing an IC, a designer may select particular cells from a library of cells and use them in a design. The library includes cells that have been designed for a given IC manufacturing process, such as complementary metal oxide semiconductor (CMOS) fabrication. The cells generally have a fixed height but a variable width, which enables the cells to be placed in rows. Cells typically do not change from one design to the next, but the way in which they are interconnected will, to achieve the desired function in a given design. By being able to select the cells from the library for use in the design, the designer can quickly implement a desired functionality without having to custom design the entire integrated circuit from scratch. Thus, the designer will have a certain level of confidence that the integrated circuit will work as intended when manufactured without having to worry about the details of the individual transistors that make up each cell.
Cells are normally designed so that routing connections between cells can be made as efficiently as possible. Routing in an IC design is accomplished through routing elements, such as wires in one or more metal layers. Each metal layer is separated from other metal layers by insulating layers, and vias connect one metal layer to another. These routing elements perform at least two functions: they connect individual transistors that make up a cell, and they connect cells to each other globally (i.e., on a chip-level) to implement the desired functionality of the integrated circuit. For example, clock signals, reset signals, test signals, and supply voltages may be carried through these routing elements. A well-designed cell layout minimizes congestion in routing global interconnections, which reduces the number of metal layers in or overall size of an integrated circuit layout.
Typically, the design layout is checked against a set of design rules in a design rule check (DRC). The created design layout must conform to a complex set of design rules in order, for example, to ensure a lower probability of fabrication defects. The design rules specify, for example, how far apart the geometries on various layers must be, or how large or small various aspects of the layout must be for successful fabrication, given the tolerances and other limitations of the fabrication process. A design rule may be a minimum spacing amount between geometries and is typically closely associated to the technology, fabrication process and design characteristics. For example, different minimum spacing amounts between geometries can be specified for different sizes of geometries. DRC is a time-consuming iterative process that often requires manual manipulation and interaction by the designer. The designer performs design layout and DRC iteratively, reshaping and moving design geometries to correct all layout errors and achieve a relatively DRC clean (violation free) design.
Most design technologies include via enclosure rules to ensure that both top and bottom metals enclose the via by a certain amount. In other words, such an enclosure rule ensures that each metal layer overlaps a via with a certain amount of extra metal to ensure that the via provides a good connection between the two metal layers once fabricated. The design rule specifying the extra amount of metal around each via may be referred to as a via enclosure rule.
As shown in the prior art standard cell 10 of FIGS. 1A-B, a standard cell architecture will have metal 1 (M1) pins 12A-B that are primarily on a vertical orientation and connected by horizontal metal 2 (M2) wire 14 (FIG. 1B). Standard cell 10 further includes a set of power rails 16A-B and a plurality of routing tracks 18A-D. Standard cell 10 further includes a plurality of pin access points 20A-D distributed between M1 pins 12A-B, as shown. In this case, standard cell 10 is limited to only two access points for each of M1 pins 12A and 12B, which causes a significant impact on routing efficiency and thus chip size.
Furthermore, M1 pins 12A-B have a width ‘W’, which is approximately the same as the width of via 1 (V1). However, M1 pin 12B extends below V1 and M2 wire 14 a distance 1′ to ensure V1 enclosure rules are satisfied. As a result, there is insufficient via enclosure for M1 pins 12A-B, e.g., in an area ‘X’ along routing tracks 18A and 18D.
One prior art solution to address this problem is shown by standard cell 30 in FIGS. 2A-B. Standard cell 30 provides an L-shaped pin formed by an M1 patch 32 that extends horizontally along M2 wire 34. As shown, standard cell 30 contains M1 pins 36A-B that are primarily on a vertical orientation and connected by M2 wire 34. Standard cell 30 further includes a plurality of pin access points 38A-D distributed between M1 pins 36A-B, as shown. In this case, V1 is positioned on M1 patch 32 to utilize the bottom pin access point of M1 pin 36B, e.g., along routing track 40D. Sufficient via enclosure is provided on both sides of V1, as represented by distances D1 (FIG. 2B). However, this architecture requires V1 to be positioned outside the boundaries of metal pin 36B, which increases the number of DRC errors, and is difficult to implement in reality. Therefore, what is needed is a solution to at least this deficiency of the prior art.